1. Field of the Invention
This invention relates to phase fluctuation generation that can be used, for example, for measuring the transmission quality in a transmission apparatus or a trunk network adaptable to a high-speed digital communication system.
2. Description of the Related Art
In recent years, development of communication technologies to support speeding up transmission and a large transmission capacity has become an urgent necessity with a surge in demand for information communications. Establishment of a measurement technique for evaluating such communication technologies is also demanded. As measurement for evaluating the transmission quality in a transmission system of a transmission apparatus, a trunk network, etc., adaptable to a high-speed digital communication system, phase difference measurement is executed for detecting jitter (high-frequency component) and wander (low-frequency component) of phase fluctuation components occurring in the transmission system.
To evaluate the clock system of each apparatus of the transmission apparatus, the trunk network, etc., used with the transmission system adaptable to the high-speed digital communication system, phase fluctuation needs to be given to a transmission data signal input to the apparatus whose clock system is to be measured; hitherto, a phase-locked loop (PLL) circuit has been used to give the jitter or wander of phase fluctuation to a transmission clock signal for generating the transmission data signal.
FIG. 6 shows a circuit configuration example of a phase fluctuation generation circuit 100 for giving phase fluctuation with PLL circuits in a related art. In the phase fluctuation generation circuit 100 shown in FIG. 6, a PLL circuit 101 at the first stage multiplies the frequency of a 32-kHz (kilohertz) input signal by 270 and outputs a 8.64-MHz (megahertz) signal and a PLL circuit 102 at the second stage multiplies the frequency of the 8.64-MHz signal input from the PLL circuit 101 by 288 and outputs a 2488.32-MHz signal.
A circuit configuration for giving phase fluctuation to the 2488.32-MHz output signal is contained in the PLL circuit 101. FIG. 7 shows the circuit configuration. The PLL circuit 101 shown in FIG. 7 is made up of a phase detector (PD) 111, a loop filter circuit 114 consisting of an addition circuit 112 comprising resistors R1 and R2 and an inverting amplifier 113 with a resistor R3 and a capacitor C1 connected, a voltage-controlled oscillator (VCO) 115, and a divider 116.
The phase detector (PD) 111 detects a phase difference between an input signal (32 KHz) used as a reference signal and a division signal input from the divider 116 and outputs a phase difference signal of the pulse width corresponding to the phase difference to the loop filter circuit 114. If a phase fluctuation signal (modulated signal with sine wave) is not input to the resistor R2, the loop filter circuit 114 inverts and amplifies the phase difference signal input via the resistor R1 and outputs the signal to the voltage-controlled oscillator 115, which then maintains the frequency of an output signal at 8.64 MHz in response to voltage fluctuation of the inverted and amplified signal input from the inverting amplifier 113. That is, the PLL circuit 101 also outputs the output signal of the voltage-controlled oscillator 115 to the divider 116 and feeds a division signal provided by dividing the output signal of the voltage-controlled oscillator 115 by 270 into the phase detector 116, thereby always correcting the phase fluctuation component for maintaining the frequency of the output signal constant.
In the loop filter circuit 114, if a phase fluctuation signal (modulated signal with sine wave) is input to the resistor R2, the voltage amplitude at the input time is added to the voltage provided by integrating the phase difference signal input to the resistor R1 as phase component and the result is output from the inverting amplifier 113 for fluctuating the output frequency of the voltage-controlled oscillator 115. Output of the voltage-controlled oscillator 115 is divided by 270 by the divider 116 and the result is fed back into the phase detector 111, whereby the phase difference signal input to the resistor R1 operates the PLL circuit 101 so as to cancel the voltage input to the resistor R2. Consequently, the phase difference between the reference clock signal and the fed-back clock signal input to the phase detector 111 becomes a value proportional to the voltage input to the resistor R2, thus an output signal containing the phase difference controlled at the voltage input to the resistor R2 is output from the voltage-controlled oscillator 115.
The configuration of the PLL circuit 101 enables the phase fluctuation generation circuit 100 to generate wander in the output signal.
However, since the phase fluctuation generation circuit 100 comprising the PLL circuits in the related art is of the circuit configuration for adding phase fluctuation for generating wander by the analog addition circuit contained in the loop filter circuit 114, the maximum variable amount of the phase fluctuation is determined in the phase comparison frequency range of the PLL circuit 101, thus the PLL circuit 101 for setting the input signal to a low frequency of about 32 KHz becomes necessary and the phase fluctuation amount cannot be set as desired; this is a problem.
Thus, for example, in a transmission system adapted to the 2.5-GHz bit rate in SDH (Synchronous Digital Hierarchy) defined in 0.171, 2 of ITU-T (International Telecommunication Union) Recommendation, very large wander of 57600 UI (unit interval) needs to be given to the apparatus on which measurement is to be made. However, since the maximum variable amount of the phase fluctuation is limited in the range of phase-comparable frequencies of the phase comparator 101 in the phase fluctuation generation circuit 100 comprising the PLL circuits in the related art, the amplitude of the modulated signal added to the addition circuit contained in the loop filter circuit 114 is also limited and it is difficult to generate very large wander.
In general, according to one aspect, a phase fluctuation generation circuit includes a phase detection circuit for detecting a phase difference between a reference clock signal and a fed-back clock signal and outputting a phase difference signal. A conversion circuit is provided for converting the phase difference signal output from the phase detection circuit into a predetermined voltage signal. A voltage-controlled oscillation circuit outputs a clock signal of a predetermined oscillation frequency in response to a voltage value of the voltage signal output from the conversion circuit. A modulated signal generation circuit generates a modulation control signal to fluctuate a phase of the fed-back clock signal. A dividing circuit operating at clock timing of the clock signal output from the voltage-controlled oscillation circuit multiplexes the modulation control signal output from the modulated signal generation circuit and outputs the fed-back clock signal to the phase detection circuit.
Some implementations may include one or more of the following features. The dividing circuit can include a multiplexer. The modulated signal generation circuit can include a signal source for generating a sine wave signal of a predetermined amplitude at a predetermined frequency, an A/D conversion circuit for sampling the sine wave signal output from the signal source at a predetermined timing and converting the signal into a predetermined digital signal, and a bit shift circuit for converting the digital signal output from the A/D conversion circuit into a modulation control signal containing parallel bits cyclically shifted and outputting the modulation control signal. The dividing circuit can multiplex the modulation control signal containing parallel bits output from the bit shift circuit to convert the signal into a fed-back clock signal containing serial bits and swing the phase of the serial bits of the fed-back clock signal in response to the shift state of the bit string in the modulation control signal.
In another aspect, a phase fluctuation generation method comprises a phase detection step including detecting a phase difference between a reference clock signal and a fed-back clock signal and outputting a phase difference signal. A conversion step includes converting the phase difference signal output from the phase detection step into a predetermined voltage signal. A voltage-controlled oscillation step includes outputting a clock signal of a predetermined oscillation frequency in response to a voltage value of the voltage signal output from the conversion step. A modulated signal generation step includes generating a modulation control signal for fluctuating a phase of the fed-back clock signal. A dividing step includes operating at clock timing of the clock signal output from thed voltage-controlled oscillation step for multiplexing the modulation control signal output from the modulated signal generation step and outputting the fed-back clock signal.
One or more of the following advantages may be present in some implementations. A wide range of phase fluctuation can be provided to the output signal independently of the phase comparison frequency. For example, it is possible to provide very large wander to a transmission system for transmitting at a high bit rate. The phase variable amount can be set independently of the phase comparison frequency based on the reference clock signal input to the phase detection circuit, so that the division ratio of the fed-back clock signal can be set smaller than that in the PLL circuit in the related art, facilitating design of the phase fluctuation generation circuit.
Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.